Op-Amp Lab Sample: Inverting, Non-Inverting, Multistage

For information and reference only – not to be submitted as your own work.

This is a results-section extract for a three-circuit op-amp lab: an inverting amplifier, a non-inverting amplifier and a multistage circuit, all built around the 741. It covers hand calculations, waveform sketches and a Multisim checklist. You can browse more engineering assignment samples on our site, and the method is explained step by step in how to calculate op-amp output voltage for a lab report.

One point before the numbers. The Circuit 3 resistor values in the original drawing are hard to read, so the values used below are illustrative. The method is what matters: it carries over to whatever values your own sheet shows.

Setup and assumptions

All three circuits use a 741 with supplies of +12 V and −12 V. Every source is a sine wave of 1 V peak at 10 kHz, and the oscilloscope is connected across the input and the output. Pin use follows the standard 8-pin package: pin 2 inverting input, pin 3 non-inverting input, pin 4 V−, pin 6 output, pin 7 V+. Pins 1 and 5 are the offset-null pair and pin 8 is not connected.

Two assumptions apply throughout. First, the op-amp is ideal for the hand calculation: infinite open-loop gain, so the inverting input is a virtual earth. Second, the output cannot go beyond the supply rails. The Texas Instruments uA741 datasheet gives output swing only for ±15 V supplies (minimum ±10 V into 2 kΩ and ±12 V into 10 kΩ), and has no figure for ±12 V. So the clipping level of ±10 V used below is an assumption (illustrative), to be checked against your simulation.

Task 1: Hand calculations

Circuit 1: inverting amplifier

With R1 = 1 kΩ at the input and R2 = 10 kΩ in feedback, the closed-loop gain is −R2/R1.

Quantity Working Result
Voltage gain −10 kΩ / 1 kΩ −10
Ideal output peak 10 × 1 V 10 V peak
Phase of output negative gain 180° from input
Within ±12 V rails? 10 V < 12 V Yes, but close to the practical limit

So the ideal output is 10 sin(ωt + 180°) volts, which is −10 sin(ωt). The input and output peaks are 1 V and 10 V, and the output is a mirror image of the input about the time axis.

Circuit 2: non-inverting amplifier

The input goes to pin 3, R1 = 1 kΩ runs to ground and the feedback resistor is 10 kΩ. The drawing also shows an extra 10 kΩ resistor. It is treated here as a load on the output, so it does not change the ideal gain, and it is ignored in the gain calculation. It does matter for output current, which is why it is worth stating.

Quantity Working Result
Voltage gain 1 + 10 kΩ / 1 kΩ +11
Ideal output peak 11 × 1 V 11 V peak
Phase of output positive gain 0° (in phase)
Practical output (assumed ±10 V limit, illustrative) 11 V exceeds limit Clipped at about 10 V peak

Circuit 3: multistage (illustrative values)

Two inverting input stages feed a third inverting stage that sums them. The values below are illustrative, chosen to match the rough ratios visible on the drawing.

Stage Illustrative values Gain Output (1 V peak in)
Stage A (inverting) Rin 2 kΩ, Rf 8 kΩ −4 −4 sin(ωt) V
Stage B (inverting) Rin 4 kΩ, Rf 8 kΩ −2 −2 sin(ωt) V
Stage C (summing, inverting) R(A) 3 kΩ, R(B) 10 kΩ, Rf 10 kΩ −3.33 from A, −1 from B see below

The summing stage output is Vout = −Rf × (VA/R(A) + VB/R(B)). Substituting: Vout = −10 kΩ × (−4/3 kΩ + −2/10 kΩ) sin(ωt) = −(−13.33 − 2) sin(ωt) = +15.33 sin(ωt) volts. Two inversions cancel, so the final output is in phase with the input.

A peak of 15.33 V cannot exist on ±12 V rails. Stage C would clip. A useful extra line in your report is the scaled case: with 0.5 V peak sources (illustrative) the same arithmetic gives 7.67 V peak, which stays inside the limit and shows the design works when the input is smaller.

Stuck in This Assignment? Deadlines Are Near?

Expected waveforms

Draw the input and output on the same time axis. At 10 kHz the period is 100 µs, so one division of 25 µs gives four divisions per cycle and keeps the sketch tidy.

Circuit Input Ideal output peak Phase Practical note
1 Inverting 1 V pk, 10 kHz 10 V 180° Near the swing limit; slew rate is marginal
2 Non-inverting 1 V pk, 10 kHz 11 V 0° Flat-topped near the assumed ±10 V
3 Multistage (illustrative) 1 V pk each, 10 kHz 15.33 V 0° Clips; works unclipped at 0.5 V input

Task 2: Simulation checklist (Multisim)

NI Multisim uses SPICE-based simulation, so the 741 model includes the limits that hand calculations ignore. Work through these steps and capture each screenshot.

  1. Place the 741 from the component database, add dual DC supplies of ±12 V and a ground. Confirm pins 4 and 7 are wired to V− and V+.
  2. Build Circuit 1 with R1 = 1 kΩ and the 10 kΩ feedback resistor. Set the AC voltage source to 1 V peak, 10 kHz.
  3. Connect the oscilloscope channel A to the input and channel B to the output. Set the time base near 25 µs/div and use separate volts/div settings so both traces are readable.
  4. Run the simulation. Screenshot the schematic, then the scope trace, then the measured output voltage (a multimeter or the scope cursors).
  5. Repeat for Circuit 2, including the extra 10 kΩ as a load, and for Circuit 3 with your own legible values.
  6. Run once with a reduced input (for example 0.5 V peak) to show the clipping disappears.
Screenshot What it must show
Schematic All pin connections, values, supplies and scope probes
Output measurement Peak value read with cursors or a meter, with units
Input and output waveforms Both channels together, with phase relationship visible

Discussion: why simulation may differ from the calculation

Supply rails. An op-amp output cannot reach the supply voltage. The datasheet quotes its guaranteed swing at ±15 V, so with ±12 V supplies expect clipping a volt or two inside the rails. The 11 V peak of Circuit 2 is the most likely casualty.

Slew rate. The datasheet lists a slew rate of 0.5 V/µs at unity gain (±15 V, 25°C). A sine of peak Vp and frequency f has a maximum rate of change of 2πfVp. For Circuit 1: 2π × 10,000 × 10 = 628,319 V/s, or about 0.63 V/µs. That is more than 0.5 V/µs, so the output cannot follow the ideal sine and will look slightly triangular. For Circuit 2 at 11 V the figure is about 0.69 V/µs, worse still. Rearranged, the largest undistorted amplitude at 10 kHz is 0.5 V/µs ÷ (2π × 10 kHz), about 8 V peak. This is the datasheet figure for specific test conditions, so treat it as indicative rather than exact.

Bandwidth. The datasheet shows open-loop gain against frequency rather than quoting a single gain-bandwidth number in its text. The principle still holds: the closed-loop bandwidth falls as gain rises, so the gain-of-11 circuit has less headroom than the gain-of-10 one. Read the value from the open-loop gain curve in your datasheet and compare it with the 10 kHz signal.

Conclusion

The ideal calculations give −10 for the inverting stage (10 V peak, 180° shift), +11 for the non-inverting stage (11 V peak, in phase) and an illustrative 15.33 V peak for Circuit 3. In practice, rail limits and slew rate mean the real or simulated waveforms will be lower or distorted. Reporting both the ideal and the practical result, and explaining the gap, is what earns the analysis marks.

If you want help structuring an engineering lab report, see our engineering assignment help and report writing help pages. A related electronics brief is covered in the intermediate electronic devices and digital systems brief.

About the expert

Ahmad Firdaus completed a Bachelor’s degree in Electrical Engineering from Universiti Teknologi Malaysia. His listed subject expertise covers assignments in electrical engineering, electronics, power systems, control systems and more.

References

National Instruments. (n.d.). Multisim. NI. https://www.ni.com/en-my/shop/product/multisim.html

Sedra, A. S., Smith, K. C., Carusone, T. C., & Gaudet, V. (2020). Microelectronic circuits (International 8th ed.). Oxford University Press.

Texas Instruments. (n.d.). uA741 general-purpose operational amplifier [Data sheet]. https://www.ti.com/lit/ds/symlink/ua741.pdf

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