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| Course Coordinator | DR Mohd Hezri Bin Marzaki |
T-DF Assignment Declaration Form (1/2020 version #003)
| QUESTION
|
Mark(s) | Grade | ||||
| F, D- , D | C-, C , C+ | B-, B, B+ | A-, A | |||
| Poor | Mediocre | Good | Outstanding | |||
| Weight | 0.25 | 0.5 | 0.75 | 1 | ||
| Lab 1 | 1.Write the short introduction, some explanation on TRiLOGI software and experimental procedure | 10 | The question answered is erroneous or irrelevant
|
The question answered is partially identified and is stated in a somewhat unclear manner. | The question answered is identified but is stated in a somewhat unclear manner. | The question answered is identified but is clearly identified and stated. |
| 2. By using the TRiLOGI software, simulate the steps and generate the ladder diagram. You should capture results based on each condition of your simulations and present them in your report. You may use “Print Screen” to capture your simulation results. You must also include the ladder diagram generated from your simulations in your report. | 30 | Needed diagrams are missing OR are missing important labels. | Diagrams are included and are labelled. | Diagrams are included and are labelled neatly and accurately. | Clear, accurate diagrams are included and make the experiment easier to understand. Diagrams are labelled neatly and accurately. | |
| 3. Write a short report to discuss your answers. discussion on explanation on ladder logic and the results you obtain at every stages of the simulation. | 10 | Report illustrates inaccurate understanding of ladder logic, concepts underlying the lab. | Report illustrates a limited understanding of ladder logic, concepts underlying the lab. | Report illustrates an accurate understanding of most ladder logic, concepts underlying the lab. | Report illustrates an accurate and thorough understanding of ladder logic, concepts underlying the lab. | |
Ladder Logic Programming Using TRiLOGI
To explain the concept and procedure in designing the ladder diagram (CLO1/3, P2)
TRiLOGI
Below is a brief procedure to guide you to download and install the TriLogi freeware which will be used during the de-couple lab session for TEL203/05. This freeware is only valid within seven days after installation. Hence it can only be installed a few days prior to the de-couple lab session. Please kindly follow the procedures as listed below:-
http://www.triplc.com/iTrilogi6Edu/
Password: LadderBasic2009
By using the TRiLOGI software, simulate the steps and generate the ladder diagram based on narrative statement, input and output port table and flowchart below. You should capture results based on each condition of your simulations and present them in your report. You may use “Print Screen” to capture your simulation results. You must also include the ladder diagram generated from your simulations in your report.
1. Narrative Statement
I) Start the bottle conveyor
ii) When a bottle is in position
a. Stop the conveyor
b. Open the output valve
iii) When the bottle is full
a. Close the output valve
iv) Repeat i)
2. Input and Output Port Table
| Input Port | Output Port | ||
| X0 | Start | Y0 | Conveyor Motor |
| X1 | Stop | Y1 | Valve |
| X2 | Sensor BP | ||
| X3 | Sensor BF | ||
3. Flow chart
Write a short report to discuss your answers. Your report should contain a short introduction, some explanation on ladder logic, your experimental procedure, and the results you obtain at every stage of the simulation.
| QUESTION
|
Mark(s) | Grade | ||||
| Poor | Mediocre | Good | Outstanding | |||
| Weight | 0.25 | 0.5 | 0.75 | 1 | ||
| Lab 2 | 1.Write the short introduction, some explanation on Wheatstone bridge simulation and experimental procedure | 5 | The question answered is erroneous or irrelevant
|
The question answered is partially identified and is stated in a somewhat unclear manner. | The question answered is identified but is stated in a somewhat unclear manner. | The question answered is identified but is clearly identified and stated. |
| 2.You are required to include a picture of circuit output results in your report
-Measure and record (screenshot) the value of voltage between point V1 and V3?. -Verified the answer in (1) with the theoretical calculation. -Explain why is voltage between point V1 and V3 has minus sign? -Find value of Rx if R1=1 kΩ, R2=3 kΩ and R3=4 kΩ under balance condition. (measure and record (screenshot) |
15 | The question answered is erroneous or irrelevant.
Needed diagrams are missing OR are missing important labels. |
The question answered is partially identified and is stated in a somewhat unclear manner.
Diagrams are included and are labelled. |
The question answered is identified but is stated in a somewhat unclear manner.
Diagrams are included and are labelled neatly and accurately. |
The question answered is identified but is clearly identified and stated.
Clear, accurate diagrams are included. Diagrams are labelled neatly and accurately. |
|
| 3. Write a discussion for this lab. The discussion should be as detailed as possible covering the following aspects:
-Operation of Wheatstone bridge simulation |
5 | Report illustrates inaccurate understanding of limitation circuit design underlying the lab. | Report illustrates a limited understanding of limitation circuit design underlying the lab. | Report illustrates an accurate understanding of most limitation circuit design concepts underlying the lab. | Report illustrates an accurate and thorough understanding of limitation circuit design concepts underlying the lab. | |
Wheatstone bridge simulation
To construct and analyze Wheatstone bridge using Multisim Live (Drag and Drop) (CLO1/2/3, C4, P5)
Multisim Live
1. Open the following lab:
2. Click on sign up to create free account or login using an existing account.
3. After you create/ log in the account. Click on CIRCUITS>MyCircuits
4. A blank workspace will appear. Drag and drop the following items from the leftside panel into the workspace.
i) Ground
ii) DC Voltage
iii) Resistor
5. Construct the circuit as shown in figure below. Ensure the circuit is properly connected
Tips on how to place voltage indicator: Drag and drop the junction from the leftside panel into the workspace
i) Connect the 1st junction to wire 1
ii) Connect the 2nd junction to wire 3
iii) Place voltage indicator at junction 1
iv) Click at V-, and place at junction 2
v. Click the play button, and observed the reading.
Write a short report to discuss your answers. Your report should contain a short introduction, some explanation on Wheatstone bridge simulation, your experimental procedure, and the results you obtain at every stages of the simulation
| QUESTION | Mark(s) | Grade | ||||
| Poor | Mediocre | Good | Outstanding | |||
| Weight | 0.25 | 0.5 | 0.75 | 1 | ||
| Lab 3 | 1.Write the short introduction, some explanation on binary weighted resistor & R/2R ladder and experimental procedure
|
5 | The question answered is erroneous or irrelevant
|
The question answered is partially identified and is stated in a somewhat unclear manner. | The question answered is identified but is stated in a somewhat unclear manner. | The question answered is identified but is clearly identified and stated. |
| 2.Complete the tables in result section. You are required to include a picture of circuit output results in your report
|
15 | Unable to complete table. Needed diagrams are missing OR are missing important labels. | Partially complete the table.
Diagrams are included and are labelled. |
Almost complete the table.
Diagrams are included and are labelled neatly and accurately. |
Complete all the table. Clear, accurate diagrams are included. Diagrams are labelled neatly and accurately. | |
| 3. Write a discussion for this lab. The discussion should be as detailed as possible covering the following aspects:
-Operation of binary weighted resistor and R/2R ladder
|
5 | Report illustrates inaccurate understanding of limitation circuit design underlying the lab. | Report illustrates a limited understanding of limitation circuit design underlying the lab. | Report illustrates an accurate understanding of most limitation circuit design concepts underlying the lab. | Report illustrates an accurate and thorough understanding of limitation circuit design concepts underlying the lab. | |
Title:
DAC simulation by using binary weighted resistor and R/2R ladder
Objective:
To construct and analyze binary weighted resistor and R/2R ladder using Multisim Live (Drag and Drop) (CLO1/2/3, C4, P5)
Software:
Multisim Live
Procedure:
1. Open the following lab:
2. Click on sign up to create free account or login using an existing account.
3. After you create/ log in the account. Click on CIRCUITS>MyCircuits
4. A blank workspace will appear. Drag and drop the following items from the leftside panel into the workspace.
i) Ground
ii) DC Voltage
iii) SPST
iv) 3 Terminal Opamp
v) Resistor
Part 1: 3-bit binary weighted resistor
1. Construct the circuit as shown in figure below. Ensure the circuit is properly connected
2. Click the play button, and observed the reading.
3. Modify circuit above into 4-bit binary weighted resistor. Observed and record the reading
Part 2: 3-bit R/2R ladder
1. Construct the circuit as shown in figure below. Ensure the circuit is properly connected
2. Click the play button, and observed the reading.
3. Modify circuit above into 4-bit R/2R ladder. Observed and record the reading.
Part 1: Binary weighted resistor and R/2R ladder
Record the value of Vout in for 3bit-binary weighted resistor table below:
| S1 | S2 | S3 | Vout |
| 1 | 1 | 1 | |
| 1 | 1 | 0 | |
| 1 | 0 | 1 | |
| 1 | 0 | 0 | |
| 0 | 1 | 1 | |
| 0 | 1 | 0 | |
| 0 | 0 | 1 | |
| 0 | 0 | 0 |
Record the value of Vout for 4bit-binary weighted resistor table below:
| S1 | S2 | S3 | S4 | Vout |
| 1 | 1 | 1 | 1 | |
| 1 | 1 | 1 | 0 | |
| 1 | 1 | 0 | 1 | |
| 1 | 1 | 0 | 0 | |
| 1 | 0 | 1 | 1 | |
| 1 | 0 | 1 | 0 | |
| 1 | 0 | 0 | 1 | |
| 1 | 0 | 0 | 0 | |
| 0 | 1 | 1 | 1 | |
| 0 | 1 | 1 | 0 | |
| 0 | 1 | 0 | 1 | |
| 0 | 1 | 0 | 0 | |
| 0 | 0 | 1 | 1 | |
| 0 | 0 | 1 | 0 | |
| 0 | 0 | 0 | 1 | |
| 0 | 0 | 0 | 0 |
Part 2:
Record the value of Vout for 3-bit R/2R ladder table below:
| S1 | S2 | S3 | Vout |
| 1 | 1 | 1 | |
| 1 | 1 | 0 | |
| 1 | 0 | 1 | |
| 1 | 0 | 0 | |
| 0 | 1 | 1 | |
| 0 | 1 | 0 | |
| 0 | 0 | 1 | |
| 0 | 0 | 0 |
Record the value of Vout for 4-bit R/2R ladder table below:
| S1 | S2 | S3 | S4 | Vout |
| 1 | 1 | 1 | 1 | |
| 1 | 1 | 1 | 0 | |
| 1 | 1 | 0 | 1 | |
| 1 | 1 | 0 | 0 | |
| 1 | 0 | 1 | 1 | |
| 1 | 0 | 1 | 0 | |
| 1 | 0 | 0 | 1 | |
| 1 | 0 | 0 | 0 | |
| 0 | 1 | 1 | 1 | |
| 0 | 1 | 1 | 0 | |
| 0 | 1 | 0 | 1 | |
| 0 | 1 | 0 | 0 | |
| 0 | 0 | 1 | 1 | |
| 0 | 0 | 1 | 0 | |
| 0 | 0 | 0 | 1 | |
| 0 | 0 | 0 | 0 |
Write a short report to discuss your answers. Your report should contain a short introduction, some explanation on binary weighted resistor and R/2R ladder, your experimental procedure, and the results you obtain at every stage of the simulation.
End of Course Assessment 2
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